(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes for forming DRAMs.
(2) Description of Prior Art
Computer memory consists of vast arrays of storage cells which can be addressed by wordlines and bitlines. The most commonly used cell design used in current dynamic-random-access-memories(DRAMs) comprises a transfer gate, usually an MOS field-effect-transistor(MOSFET), and a storage node consisting of a capacitor. DRAM cells are, by necessity of high density requirements, of the simplest design possible and to this end, the MOSFET-capacitor combination serves quite well.
In order to maintain a sufficiently high capacitance of the storage capacitor in wake of constantly shrinking cell size, many variations of the cell configuration have evolved. These include contorting the capacitor within the confines of the cell in order to maintain a sufficient plate area. The stacked capacitor(STC) configuration is most commonly used. One design for this capacitor comprises a cylindrical structure having a narrow structure beginning at a contact to a transistor drain and, after rising above the level wherein bitlines and wordlines are located, enlarging to cover nearly the entire area of the cell.
In order to form the opening of this structure an etch-stop layer is required at the level where the storage plate enlarges. The function of the etch-stop layer will become clear as the embodiments of this invention are described. Typically this is a Si.sub.3 N.sub.4 layer between about 200 .ANG. and 1,500 .ANG. thick.
After the polysilicon storage plate of the stacked capacitor has been formed, the wafer is subjected to temperatures of about 700.degree. C. in order to form the capacitor dielectric. The dielectric commonly used is a composite layer of SiO.sub.2 /Si.sub.3 N.sub.4 /SiO.sub.2, referred to simply as ONO. During this thermal exposure, the Si.sub.3 N.sub.4 etch-stop layer over the surface surrounding contact openings is exposed. These openings are found primarily in the peripheral circuits of the DRAM. The high temperature during the ONO processing causes the Si.sub.3 N.sub.4 layer, which is under tensile stress, to crack at these openings. The cracks emanate from the corners of the openings and spread over a large area of the wafer, branching as well. FIG. 1 shows an angled cross section of a contact opening 50 in the periphery of a DRAM integrated circuit on wafer 10. The opening is made to an active area 11 through a Si.sub.3 N.sub.4 etch-stop layer 20 and an insulative layer 17. The wafer has been subjected to a thermal stress of 700.degree. C. to form an ONO dielectric layer in the cell array of the DRAM. Long branching cracks 52 are formed in the Si.sub.3 N.sub.4, emanating from the corners of the opening 50 and extending great distances across the wafer surface. These cracks 52 are prone to harbor adsorbed moisture and sundry contaminants, leading to reliability problems.
In regions where the Si.sub.3 N.sub.4 layer is not exposed during the ONO formation cracks do not occur. However, the subsequent formation of contact openings 60 through the Si.sub.3 N.sub.4 etch-stop layer 20 as shown in FIG. 2, present an additional problem.
An interlevel dielectric layer 62 has been deposited over the nitride layer 20 and a contact opening 60 has been etched through to the silicon active area 11. Because of the etch resistance of the Si.sub.3 N.sub.4 layer, fragmented projections 64 remain in the contact opening 60. These projections 64 shadow the opening wall just below them from subsequent barrier metal deposition producing a weakened contact.
Dennison U.S. Pat. No. 5,292,677 utilizes an Al.sub.2 O.sub.3 etch-stop layer deposited over a silicon oxide layer. The capacitor and the peripheral contacts are opened at the same time using the etch-stop layer. The exposed layer is then removed from all the openings. Dennison does not use a buried bit line as does the cell addressed by this invention. The etch-stop layer used by Dennison is at a lower level and is not used in the same way as in this invention. In Dennison, the storage poly is deposited into both the capacitor and the contact openings as in the process of this invention.
By using a timed etch, Dennison leaves insulator over the surface adjacent to the contact openings, covering the etch-stop layer. However, as will become apparent in the description of the embodiments, the process of this invention utilizes the Si.sub.3 N.sub.4 etch-stop layer a second time to halt the wet etch which exposes the completed storage poly plates. This leaves un-covered Si.sub.3 N.sub.4 adjacent to the contact openings which cracks during the ONO deposition.
Hong U.S. Pat. No. 5,464,785 shows the use of Si.sub.3 N.sub.4 as a sacrificial layer in the manufacture of an EPROM having ONO. However the Si.sub.3 N.sub.4 is deposited after the ONO is formed and is not subjected to high temperature.